Synchronous FSM using D flip-flops with combinational logic gates implements a four-state controller driven by button input and clock signal. Q1 and Q0 outputs from dual D flip-flops feed back through OR and AND gates to generate next-state inputs D1 and D0, with an inverter providing NOT(Q0) for state transition logic. The circuit transitions between states 00, 01, 10, and 11 based on button press conditions evaluated at each clock edge. Fork this diagram to customize state transitions, modify gate logic, or adapt the FSM for your specific control application. This topology demonstrates synchronous design principles: all state changes occur on clock edges, eliminating race conditions and ensuring predictable behavior.