I2S transmitter RTL datapath and controller implements a complete digital audio serialization pipeline for FPGA designs. The architecture combines edge detection and finite state machine control to synchronize left and right audio channels with BCLK and LRCLK clock domains, routing 24-bit stereo samples through a 32-bit shift register for MSB-first serial output. The datapath uses a 2:1 multiplexer to select between left and right audio data based on LRCLK rising edge detection, padding samples to 32 bits and shifting out one bit per BCLK falling edge. This design demonstrates best practices for audio codec integration: proper clock domain handling, deterministic bit counting, and clean separation of control logic from datapath operations. Fork this diagram to customize bit widths, add parity or CRC protection, or adapt for different audio standards like S/PDIF or TDM. The modular FSM and shift register architecture makes it ideal for teaching RTL design patterns or as a foundation for production audio interfaces.